Ever since the planar integrated circuit was invented independently by Robert Noyce and Jack Kilby in 1959, designers have sought methods to automate the process of creating the mask artwork necessary for photolithography. Originally circuit designers had to manually create accurate scale drawings of a circuit layout and separate these into mask overlays. By the late 1960's, as described in the document, “Masks Automatically,” at the Smithsonian National Museum of American History, Science Service, CD 1967051, E&MP 68.001, computer-aided design (CAD) methods had been developed so that designers could provide a circuit description in a symbolic language to a computer program that would trace the mask layers on a light table. By the mid-1970's as computers had developed to the point where bit-mapped graphics could be rendered in real-time, and as integrated circuit densities increased into the thousands of devices per chip, automated graphical layout programs began to appear that permitted the designer to directly “draw” the circuit artwork on a computer monitor using interactive graphical tools. Some of these programs are described in the papers “An Interactive Graphics System for the Design of Integrated Circuits,” presented by Infante, B., et al.; and “ICARUS: An Interactive Integrated Circuit Layout Program,” presented by Fairbairn, D. G., et al, at the 15th Conference on Design Automation in June 1978.
By the end of the 1970's, many different fabrication processes, or technologies, had been developed by different manufacturers. The earliest layout tools incorporated functions relevant to a specific fabrication process within the code, which meant that the program needed to be modified when the process changed. It quickly became apparent that technology-independence was a necessary characteristic of any program for integrated circuit layout. At the 20th Conference on Design Automation in 1983, papers by Heilweil, M. F., “Technology Rules—The Other Side of Technology Dependent Code,” and Von Ehr, G. J., “Position Paper: Role of Technology Design Rules in Design Automation,” discussed the types of information that needed to be stored in an external technology file.
By the mid-1980's almost all integrated circuit layout programs had adopted the method of storing technology-dependent information in an external technology file. Some of these programs are described in “CAD Systems for IC Design,” by Daniel et al, published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 1, January 1982, pp. 2-12; “Lyra: A New Approach to Geometric Layout Rule Checking,” by Arnold, M. H. et al, presented at the 19th Conference on Design Automation in June 1982; “Magic: A VLSI Layout System,” presented by (justerhout, J. K., at the 21st Conference on Design Automation in June 1984; and in a further paper by (justerhout, J. K., “The User Interface and Implementation of an IC Layout Editor,” published in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 3, July 1984.
At the 22nd Conference on Design Automation in 1985, Smith, P. et al, presented a general framework for a canonical technology file structure in the paper, “The VIVID System Approach to Technology Independence: the Master Technology File System”. The master technology file contains information concerning the design layers that may be drawn, as well as the graphical stipple patterns and colors for rendering the corresponding shapes on a computer monitor display. It also incorporates electrical and physical design rules to specify electrical connectivity between layers or to enforce constraints such as minimum width or spacing rules. While the exact format and contents of the technology file as implemented today in any given CAD program may vary greatly, this basic structure has become well established.
A second innovation in the development of CAD tools for integrated circuit layout, which has also become a standard feature, is the ability to create hierarchical structures and to implement standard cell libraries. An early example of a CAD system implementing cell hierarchies was presented by Edmondson, T. H., et al, “A Low Cost Hierarchical System for VLSI Layout and Verification,” at the 18th Conference on Design Automation in June 1981. In a hierarchical design, “leaf” cells representing simple combinations of gates or interconnect wiring are created as independent structures. A more complex cell can be formed by instantiating combinations of leaf cells in different positions and orientations. Not only is hierarchical design more efficient in terms of memory storage than a “flat” design, but it also permits the use of symbolic notation to represent the leaf cells in a library. This feature further leads to the possibility of automatically generating the layout from schematic or behavioral descriptions with minimal human intervention required to finalize the artwork before fabrication. U.S. Pat. No. 4,612,618 describes a canonical approach for the hierarchical, computerized design of integrated circuits.
More recently, as the need for increased circuit densities and functionalities have begun to outpace the ability of two-dimensional planar fabrication processes to produce these economically, attention has been turning to the possibilities offered by three-dimensional integration. Herein below, the term “three-dimensional integrated circuit”, or 3-D IC, refers to a circuit in which active devices layers are stacked on top of one another and electrically interconnected. The distinction is primarily related to the stacking of active devices that are formed in a semiconductor substrate. Current planar processes are inherently “three-dimensional” in that they are composed of devices upon which are formed one or more layers of dielectric and conducting materials. The text, Three-Dimensional Integrated Circuit Layout (Distinguished Dissertations in Computer Science), edited by Harter, A. C., Cambridge University Press, November, 1991, uses the term to describe the multi-layer metallization used in the planar CMOS process, and not a multi-layer device process. Herein below, a three-dimensional integrated circuit is one in which active devices, such as transistors and diodes, may be arranged both vertically and laterally.
The concept of producing three-dimensional integrated circuits to increase device density is not new. U.S. Pat. No. 4,272,880, issued in 1981 describes a method for fabricating multi-layer integrated circuits in a Silicon-on-Sapphire process. U.S. Pat. No. 4,489,478, issued in 1984 describes a method for forming a secondary semiconductor layer on top of a first with an interposing dielectric layer. However, it is only recently that manufacturing economics have spurred a renewed interest both in 3-D technology development and in 3-D circuit design. A plethora of patents have been issued in the last five years on different methodologies and approaches for 3-D integrated circuit fabrication.
U.S. Pat. No. 6,355,501 describes a method for creating 3-D circuits by stacking and aligning Silicon-on-Insulator (SOI) chips with an interposing metal layer to form interconnects. U.S. Pat. No. 6,465,892 describes a method for routing metal interconnect between vertically aligned circuit layers by boring through the substrates. U.S. Pat. No. 6,525,415 describes another method of stacking and aligning semiconductor substrates with embedded interconnect layers. U.S. Pat. No. 6,727,517 describes a vertical integration approach that involves growing semiconductor crystal grains by metal-induced lateral crystallization following patterning of amorphous silicon on deposited metal strips. U.S. Pat. No. 6,875,671 describes an approach utilizing a substrate with layers of predetermined weak and strong bond regions. Deconstructed layers of silicon circuits are fabricated on the weak bond regions and are then peeled off to form multi-layer circuits. U.S. Pat. No. 6,881,994 describes a monolithic fabrication methodology for fabricating a three-dimensional array of charge-storage devices. U.S. Pat. No. 6,943,067 describes yet another SOI-based fabrication approach incorporating a low temperature bonding method and backside/substrate contact process.
Other 3-D fabrication approaches in development have been described in the scientific literature, such as Mcllrath, L. G. et al, “Architecture for Low-Power Real-Time Image Analysis using 3D Silicon Technology,” Proceedings of SPIE AeroSense 1998, vol. 3362, August 1998; Subramanian, V., et al, “Low-Leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFT's for Vertical Integration Applications,” IEEE Electron Device Letters, vol. 20, no. 7, July 1999; Banerjee, K., et al, “3-D ICs: A Novel Chip Design for Improving DeepSubmicrometer Interconnect Performance and Systems-on-Chip Integration,” Proceedings of the IEEE, vol. 89, no. 5, May 2001; Burns, J. A., et al, “Three-Dimensional Integrated Circuits for Low-Power, High Bandwidth Systems on a Chip,” Proceedings of the 2001 IEEE International Solid State Circuits Conference, February 2001; and Patti, R., “3D: Design to Volume—A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results,” 3D Architectures for Semiconductor Integration and Packaging Symposium, June 2005.
Because technologies for fabricating 3-D integrated circuits have not yet become firmly established, relatively few designers have had the opportunity to develop 3-D circuits for fabrication. For the most part, the designers that have needed to create mask artwork for 3-D circuits have done so by implementing ad hoc workarounds within conventional CAD programs for 2-D layout. One possible workaround is to manually align cells for different stack levels by creating pseudo-3D cells, that is, having leaf cells that are the circuits for each layer. This method does not allow design rule checks or netlist extraction, however. Another method is to replicate the design layer names contained in the 2-D technology file for each of the levels in the stack. This method requires that special rules be created to specify inter-level interconnects. It also results in multiple replications of the electrical and physical design rules for each design layer and is very inefficient in terms of memory usage. The text, Three-Dimensional Integrated Circuit Layout (Distinguished Dissertations in Computer Science), by Harter, A. C., Cambridge University Press, November, 1991, describes some primitive methods for creating topologies for wiring standard cells on multiple layers, but does not provide direct methods for efficiently creating the mask artwork.
Several examples of fabricated 3-D circuits have been described in the literature. Koyanagi, M., et al, “Neuromorphic vision chip fabricated using three-dimensional integration technology,” Proceedings of the 2001 IEEE International Solid State Circuits Conference, February 2001, describes a 3-D IC containing a photoreceptor layer and two neuromorphic layers that perform operations similar to retinal bipolar and ganglion cells.
In the previously cited reference, Burns, J. A., et al, “Three-Dimensional Integrated Circuits for Low-Power, High Bandwidth Systems on a Chip,” a 3-D IC is described that has a photodiode on one layer coupled to an analog-to-digital (AID) conversion circuit on a second layer. U.S. Pat. No. 6,741,198 describes a generalized architecture for a three-layer digital imaging chip incorporating a photosensor, an A/D converter, and a digital signal processing circuit, all realized on separate circuit layers.
A 3-D radio frequency (RF) transceiver was presented by Qun, G., et al, “Three-dimensional circuit integration based on self-synchronized RF-interconnect using capacitive coupling,” 2004 Symposium on VLSI Technology, June 2004. In this device the vertical interconnects are realized through capacitive coupling of elements on separate layers. In Koob, J. C., et al, “Design of a 3D Fully-Depleted SOI Computational RAM,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 3, March 2005, a design is presented for a modular 3-D integrated processor-in-memory stack. The key feature of this design is that the same photolithography masks for each circuit level can be re-used. A hierarchical bus evaluation network senses how many layers are in the stack and generates addresses accordingly. Patti, R., “3D: Design to Volume—A Look at Various 3D Applications, Their Designs, and Ultimate Silicon Results,” 3D Architectures for Semiconductor Integration and Packaging Symposium, June 2005, describes another 3-D processor-in-memory device in which the memory elements are embedded in a circuit below the processor units.
The primary feature that is common to all of these designs is that the cell structures requiring 3-D interconnections are relatively simple. In the 3-D imaging chips, a single inter-layer interconnect is used to connect the photoreceptor to the active pixel circuit on the layer below, and only one or two 3-D interconnects are required to connect the active pixel circuit to the processing layer below it. In the 3-D integrated RF circuit, physical interconnection structures are not required. The processor-in-memory 3-D circuits are each composed of arrays of identical processing elements. Only the unit 3-D cells for each element needed to be laid out carefully and manually checked. Because of this simplicity, it was feasible, albeit time consuming, for the designers to create the mask artwork for the individual circuit layers by ad hoc methods with standard 2-D layout CAD tools.
It should be clear from this discussion that better, more automated CAD systems and methods are required for 3-D IC design before complex components can be realized. Many researchers are now investigating 3-D topologies at a higher level of abstraction than the physical layout. Routing methods for 3-D field programmable gate arrays (FPGAs) are analyzed by Hung, W. N. N., et al, “Routability checking for three-dimensional architectures,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 12, No. 12, December 2004; and Manimegalai, R., “Placement and routing for 3D-FPGAs using reinforcement learning and support vector machines,” 18th International Conference on VLSI Design, 2005. In order to reduce these systems to practice, automated tools for artwork creation and verification will have to be put in place.
In the paper by Mcllrath, L. G., “High Performance, Low Power Three-Dimensional Integrated Circuits for Next Generation Technologies,” Proceedings 2002 International Conference on Solid State Devices and Materials, Nagoya, Japan, September 2002, the requirements of an automated 3-D CAD program for generating multi-layer layouts were specified. These requirements include the need to incorporate multiple technology files for combining the technology-dependent information for different processes and the need to implement a hierarchical 3-D cell structure that can handle both vertical and lateral dependencies.